Bottom lead frame and bottom lead semiconductor package using the same
US6118174A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 1997 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Dec 17, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bottom lead frame and a bottom lead semiconductor package embodying the invention are capable of forming a multiple row pin structure. The bottom lead frame includes a plurality of first leads, and a plurality of second leads, where each lead has a bottom lead portion and an inner lead portion that is upwardly bent from the bottom lead portion. The first leads and second are arranged on opposite sides of a central portion. Each of the first leads is inserted between a pair of neighboring second leads. The bottom portions of the second leads are arranged outwardly of the bottom portions of the first leads. A lead support bar may be connected to the inner portions of the first and second leads to support the first and second leads. A semiconductor chip may be mounted on upper surfaces of either the first or the second leads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.