Low voltage reference with power supply rejection ratio
US6118266A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1999 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Sep 9, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S323/901
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method and apparatus for a voltage reference is provided. The circuit may include one or more of the following features: cascode compensation with load balancing to increase the bandwidth of the amplifier for enhanced power supply rejection ratio; PMOS and NMOS in the input stage to expand common mode, having a high gain over voltage range; current mirror using active resistors; and a start-up circuit. The voltage reference comprises an amplifier having an output, the amplifier comprising a first amplifier stage and a second amplifier stage. The amplifier further includes a power-down circuit coupled to the second amplifier stage to float the amplifier output when a power-down signal is active. The voltage reference includes a source follower, the output of the amplifier coupled to the gate of the source follower, and a bandgap circuit for providing a bandgap voltage. The voltage reference further includes a level shifter coupled to the bandgap circuit, the level shifter for providing a second stable operating point, an output of the level shifter or an output of the bandgap circuit being coupled to the first amplifier stage as an input and a current mirror. The voltage reference…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.