Method and apparatus for reducing even order distortion in differential circuits
US6118322A · kind A · utility
17Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 3, 1998 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Nov 3, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/32
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus (100) includes a differential processing circuit (135) responsive to an input signal with first and second signal components, and a signal imbalance suppressor (130) that preprocesses the input signal, prior to input to the differential processing circuit, to remove amplitude and/or phase imbalances that exist between the first and second signal components, in order to reduce even order distortion generation within the differential processing circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.