Two-phase bootstrapped CMOS switch drive technique and circuit
US6118326A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1997 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Nov 6, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/063
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit that produces a gate drive voltage for a MOS transistor switch, that receives an input voltage "on" a source terminal, includes a first input that receives the input voltage, a second input that receives a bias voltage, and a voltage storage element. A first switch connects the voltage storage element to sample one of the input voltage and the bias voltage during a first of first and second non-overlapping time intervals. A second switch connects the voltage storage element to increase the sampled voltage by another of the input voltage and the bias voltage to the gate drive voltage during the second non-overlapping time interval, while maintaining the gate drive voltage less than a breakdown voltage of the MOS transistor switch. A third switch connects the voltage storage element to provide the gate drive voltage to the MOS transistor switch such that a gate-to-source voltage of the MOS transistor switch is maintained approximately constant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.