Capacitor array for a successive approximation register (SAR) based analog to digital (A/D) converter and method therefor
US6118400A · kind A · utility
17Cited by
2References
15Claims
0Family size
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Key dates
| Filing date | Jan 20, 1998 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Jan 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A capacitor array for a Successive Approximation Register (SAR) based Analog to Digital (A/D) converter. The capacitor array is a capacitive ladder comprising a plurality of capacitive branches. Each capacitive branch is individually coupled to a separate bit of a driver circuit. Each of the plurality of capacitive branches drives an approximately same capacitive value while generating a binary weighted output voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.