DRAM bit-plane buffer for digital display system
US6118500A · kind A · utility
15Cited by
5References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 28, 1997 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Aug 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/12
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A formatter and frame buffer unit (20) for a display system (10) that uses a spatial light modulator (16) to display data formatted in bit-planes. Formatters (21) convert multi-bit pixel data to bit-plane data. The frame buffer memory (25) is comprised of conventional DRAM devices. To allow the use of DRAMs, formatters (21) operate on a number of consecutive pixels, the number of pixels being sufficient for an extended page mode form of addressing the DRAMs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.