Electrically erasable non-volatile memory cell with integrated SRAM cell to reduce testing time
US6118693A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 26, 1999 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | May 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a programmable integrated circuit, by providing a static random access memory (SRAM) cell in each electrically erasable (E.sup.2) non-volatile memory cell, testing time of circuits configured by the E.sup.2 non-volatile memory cells can be reduced substantially. In one embodiment, the SRAM cell can be included by providing a small number of transistors to recirculate the output value of an inverting buffer. During testing, a logic value is written into the SRAM cell in place of the logic value in the non-volatile storage of the E.sup.2 non-volatile memory cell. In one embodiment, the E.sup.2 non-volatile memory cell can be used in conjunction with a 1-bit shift-register. Multiple 1-bit shift registers can be used as a scan chain to scan into the SRAM cells of multiple E.sup.2 non-volatile memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.