Control scheme for shared-use dual-port predicted error array
US6118823A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 1, 1997 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Apr 1, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An MPEG-2 compliant digital video encoder system having a refinement processor for reconstructive processing for I-picture and P-picture encoding. The refinement processor includes a frame difference unit which has a predicted error array (PE array). The predicted error array comprises a shared-use array for storing both luminance data and chrominance data of a macroblock of data. The predicted error array also comprises a dual-port structure and array read control logic which allows simultaneous reading and writing of data to the array. Address selector logic controls addressing of the PE array such that writing of luminance data and chrominance data to the PE array and reading of luminance data and chrominance data from the array remains synchronous.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.