Data transfer control system determining a start of a direct memory access (DMA) using rates of a common bus allocated currently and newly requested
US6119176A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 1998 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Aug 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It is determined that, when starting of direct memory access is newly requested, whether or not the direct memory access can be started, using a rate of using the bus at the present time by data transfer performed by all the direct memory access controllers which have already started direct memory access until then and all the processors, a data transfer rate needed by the newly requested direct memory access, a size of data which is transferred in one direct memory access operation or a size of data which a memory can accept, a latency for accessing the memory, and a latency for bus-right arbitration. The newly requested direct memory access is started when it is determined that the direct memory access can be started. Starting of the newly requested direct memory access is kept waiting when it is determined that the direct memory access cannot be started. The newly requested direct memory access, which has been kept waiting, is started when any direct memory access which has already been carried out finishes, and enough capacity is free in the common bus for carrying out the newly requested direct memory access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.