System having multiple arbitrating levels for arbitrating access to a shared memory by network ports operating at different data rates
US6119196A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1997 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Jun 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/352
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for managing a buffer memory in a packet switch that is shared between multiple ports in a network system. The apparatus comprises a plurality of slow data port interfaces configured to transmit data at a first data rate between a slow data port and the buffer memory and a plurality of fast data port interfaces configured to transmit data at a second data rate between a fast data port and the buffer memory. A first level arbiter is coupled to the plurality of slow data port interfaces. The first level arbiter chooses an access request of one the slow data ports and outputs the access request. A second level arbiter is coupled to the plurality of fast data port interfaces and to the output of the first level arbiter. The second level arbiter chooses an access request from among a plurality access requests from the fast data port interfaces and the access request from the first level arbiter, and forwards the chosen access request to the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.