Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization
US6119204A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jun 30, 1998 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Jun 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes at least a first processor and a second processor that each have a respective translation lookaside buffer (TLB). In response to detection by the second processor of a TLB entry invalidation request, the second processor marks at least one memory referent instruction that is being processed by the second processor and invalidates a TLB entry in the TLB of the second processor. In response to receipt of a synchronization request at the second processor, the second processor indicates to the first processor that the second processor has invalidated the TLB entry if the second processor has completed processing the marked instruction. During the interval between receipt of the synchronization request and indicating to the first processor that the second processor has invalidated the TLB entry, the second processor continues to process instructions, including fetching instructions for processing. In this manner, the second processor is able to continue normal instruction processing during the process of TLB synchronization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.