Combined branch prediction and cache prefetch in a microprocessor
US6119222A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1997 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Dec 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor (10) and corresponding system (300) is disclosed in which prefetch of instruction or data from higher level memory (11; 307; 305) may be performed in combination with a fetch from a lower level cache (16). A branch target buffer (56) has a plurality of entries (63) associated with branching instructions; in addition to the tag field (TAG) and target field (TARGET), each entry (63) includes prefetch fields (PF0 ADDR; PF1 ADDR) containing the addresses of memory prefetches that are to be performed in combination with the fetch of the branch target address. Graduation queue and tag check circuitry (27) is provided to update the contents of the prefetch fields (PF0 ADDR; PF1 ADDR) by interrogating instructions that are executed following the associated branching instruction to detect instructions that involve cache misses, in particular the target of the next later branching instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.