Memory devices operable in both a normal and a test mode and methods for testing same
US6119249A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 1998 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Mar 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing, in parallel, a memory device including a plurality of memory cells organized into memory blocks, the memory device having a plurality of wired-OR pre-charged differential data line pairs, includes the steps of enabling a predetermined number of memory blocks at a time; writing to and reading as many bits as the predetermined number of enabled memory blocks in parallel; and detecting when both data lines of each of the wired-OR differential pairs are active at a same time, indicating that at least one bad memory cell exists within at least one of the predetermined number of enabled memory blocks. According to another embodiment, a memory device operable in both a normal and a test mode includes a plurality of memory cells organized into a plurality of blocks; at least one wired-OR pre-charged differential data line pair connected to each of the blocks; a block address decoder, the block address decoder enabling one of the plurality of blocks at a time during normal operation and more than one block at a time when the memory device is operating in test mode; and an output buffer for each of the at least one wired-OR differential pairs, the output buffer including…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.