Method and device for setting a plurality of test modes using external pins
US6119253A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 1997 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Oct 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31701
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for setting test modes in a semiconductor ship and a device suitable for the method are provided. In the method, a power voltage is externally applied to the semiconductor chip. A predetermined signal is applied to an arbitrary selected external pin of the semiconductor chip. A first-state signal is applied to the test pin and a second-state signal is applied to the test pin a predetermined time later. The signal applied to the external pin is latched by the first-state signal applied to the test pin. The second-state signal applied to the test pin, a predetermined signal output when the first-state signal applied to the test pin is shifted to the second-state signal, and the latched signal are logically combined and the combined signal is output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.