High frequency CMOS clock recovery circuit
US6121804A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1998 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Aug 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A complementary metal-oxide semiconductor (CMOS) integrated circuit that includes a clock recovery circuit. The clock recovery circuit automatically properly aligns a clock with data. A latch is used to perform the function of a flip-flop. Because the flip flop is essentially two latches, using the latch rather than the flip flop results in a circuit having one less latch. Consequently, the circuit has less propagation delay, which permits higher frequency operation. Use of the latch also reduces the load on the clock and saves power. Additionally, the clock recovery circuit uses differential logic, which decreases noise sensitivity and allows higher frequency operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.