Phase-locked loop system and method for modifying an output transition time
US6121845A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 1998 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | May 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Phase-Locked Loop (PLL) system (30) and a method for modifying the output transition time of the PLL system (30). The PLL system has an input stage (36) connected to a PLL (37). The input stage (36) includes a phase detector stage (47), a phase difference threshold stage (48), and a phase difference modification stage (49). The input stage (36) receives a reference input signal and a feedback input signal and determines the phase difference between these two input signals. If the phase difference is greater than a predetermined value, then the input stage (36) decreases the phase difference between the reference input signal and the feedback input signal. If the phase difference is less than the predetermined value, then the phase difference between the reference input signal and the feedback input signal is not modified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.