Polymer stud grid array
US6122172A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Apr 16, 1998 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Apr 16, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In order to achieve better dissipation of the heat losses, a polymer stud grid array in proposed having PA1 an injection-molded, three-dimensional substrate (S) composed of an electrically insulating polymer, PA1 polymer studs (PS) which are arranged over the area on the underneath of the substrate (S) and are integrally formed during injection molding, PA1 external connections which are formed on the polymer studs (PS) by an end surface which can be soldered, PA1 conductor runs which are formed at least on the underneath of the substrate (S) and connect the external connections to internal connections, PA1 at least one heat sink (WL) which is partially coated during the injection molding of the substrate (S), and having PA1 at least one chip or wiring element (VE) which is arranged on the heat sink (WL) and whose connections are electrically conductively connected to the internal connections. The new configuration is suitable in particular for power components or power modules in a polymer stud grid array package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.