Semiconductor memory device and method for relieving defective memory cells
US6122207A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 1999 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Mar 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of memory cell groups, the data for the plurality of memory cell groups being transmitted through mutually different buses, and a redundancy memory cell group common to the plurality of memory cell groups. The semiconductor memory device further includes a control circuit for transmitting data for one or more memory cells of the redundancy memory cell group in place of data for one or more defective memory cells in any of the plurality of memory cell groups. Each of the plurality of memory cell groups is provided corresponding to every different input/output terminal of the memory device, or the plurality of memory cell groups are provided corresponding to a common input/output terminal of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.