On-chip bus architecture that is both processor independent and scalable
US6122690A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1998 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Apr 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus in an integrated circuit uses bus interfaces to couple functional blocks to the bus in a processor independent and scalable manner. Various embodiments of the bus interfaces include a bus interface for a bus master functional block, a bus interface for a slave functional block, and a bus interface for either a bus master functional block or a slave functional block. Each bus interface includes a state machine that has at least two operational modes including a fast operational mode having two states and a normal operational mode having at least four states. A bus interface coupled to a bus master functional block implements an operational mode and a bus interface coupled to a slave functional block operates in a complementary operational mode. Each bus interface is also equipped to facilitate scaling of the address and/or data width on the bus. Various embodiments of the bus interfaces are also equipped to support multiple bus masters, broadcast writes, burst mode transfers, and/or tri-states on the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.