CPU-peripheral bus interface using byte enable signaling to control byte lane steering
US6122696A · kind A · utility
Inventors
Key dates
| Filing date | Sep 29, 1997 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Sep 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CPU-Peripheral bus interface for 64-bit local bus to 32-bit peripheral bus uses byte enable signaling to provide byte lane steering. Qbuffer logic provides a hardware interface that interfaces directly to the processor local-bus--a Qbuffer protocol using conventional byte enable signals provides lane steering to eliminate the need for separate multiplexing logic. The Qbuffer protocol signals include a BE control signal asserted by the system logic to cause the CPU to relinquish control of the byte enable control lines, such that the system control logic is able to drive the BE control lines with byte enable codes to implement lane steering for CPU-Peripheral transfers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.