Data processing apparatus with bus intervention means for controlling interconnection of plural busses
US6122699A · kind A · utility
12Cited by
14References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 1997 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | May 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention has as its object to improve the net processing speed by appropriately assigning the DMA processing time for attaining high-speed processing using hardware, and the software execution time of a CPU. By interrupting the operation of one of a CPU and a DMA processor only when a device such as an external D-RAM shared by processors such as the CPU, DMA processor, and the like, is to be accessed, the CPU operation and the DMA processing are substantially parallelly executed, thereby improving the net processing speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.