Dual-port content addressable memory
US6122706A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1993 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Dec 22, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CAM including a set of priority registers for storing information from one port and a set of non-priority registers for storing information from a second port. The CAM also includes a memory array that is coupled to both sets of registers. A port arbiter within the CAM determines which set of registers is given access to the memory array. Also described is a method for controlling access to the memory array. A lock interval is indicated before the priority registers initiate access to the memory array. During the lock interval, access to the memory by the non-priority registers is delayed if the access cannot be completed before the priority registers begin access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.