Content addressable memory system with self-timed signals and cascaded memories for propagating hit signals
US6122707A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 1997 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Sep 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a plurality of content addressable memory (CAM) arrays and a plurality of logic circuits. The logic circuits are connected to a commonly shared bus. Each of the logic circuits is associated with the respective CAM array. Each of the CAM arrays provides search results (hit, match address and multiple match) in a search operation in response to a clock signal. The hit signals provided from the CAM arrays to the respective logic circuits. Each logic circuit provides an OR logic output signal from a hit signal input from an upstream logic circuit and the hit signal provided by the CAM array associated with that logic circuit, in response to a self-timed signal which is delayed in time from the clock signal. The OR logic output signal provided by the logic circuit is provided to a downstream logic circuit. Thus, the furthest downstream logic circuit provides a hit result of the system in a search operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.