Intelligent subsystem interface for modular hardware system
US6122747A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 1997 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Sep 5, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single chip application specific integrated circuit (ASIC) which provides a flexible, modular interface between a subsystem and a standard system bus. The ASIC includes a microcontroller/microprocessor, a serial interface for connection to the bus, and a variety of communications interface devices available for coupling to the subsystem. A three-bus architecture, utilizing arbitration, provides connectivity within the ASIC and between the ASIC and the subsystem. The communication interface devices include UART (serial), parallel, analog, and external device interface utilizing bus connections paired with device select signals. A low power (sleep) mode is provided as is a processor disable option.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.