Metallization structure and method for a semiconductor device
US6124189A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 1997 |
| Grant date | Sep 26, 2000 |
| Priority date | — |
| Expiry date | Mar 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a metal-strapped polysilicon gate and for simultaneously forming a strapped-metal polysilicon gate and a metal contact filling includes the steps of forming a gate dielectric layer on a surface of a silicon substrate; forming a polysilicon layer on the gate dielectric layer; forming a first insulating layer on the polysilicon layer; forming insulating spacers on either side of the polysilicon layer and the first insulating layer; and forming ion implantation regions in the surface of the silicon substrate. Next, a second insulating layer is deposited on the silicon substrate, and the second insulating layer is polished using chemical mechanical polishing to planarize the upper surface of the second insulating layer with the upper surface of the first insulating layer as a polishing stopper. Then, a contact hole is formed in the second insulating film, wherein the contact hole is laterally spaced from the polysilicon layer and the first insulating layer. Subsequent steps include: removing the first insulating layer, thereby forming an unfilled region above the polysilicon layer; depositing a metal such as tungsten in the unfilled region and the contact hole; and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.