Method of fabricating an unlanded via
US6124200A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1999 |
| Grant date | Sep 26, 2000 |
| Priority date | — |
| Expiry date | Jul 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76801
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an unlanded via. A substrate has a metal layer formed thereon and an ARC layer is formed on the metal layer. A liner dielectric layer is formed on the ARC layer and the sidewall of the metal layer, and an insulating material layer is formed on the insulating dielectric layer. The insulating material layer is then etched back, so a surface of the insulating material layer lower than the ARC layer surface is formed. Thereafter, a protective layer is formed on the insulating material layer and the metal layer, in which the protective layer is different from the liner dielectric layer. An IMD layer is formed on the protective layer. Using the liner dielectric layer as an etching stop layer, the IMD layer and the protective layer are patterned, and then the liner dielectric layer on the metal layer is removed, such that an unlanded via opening is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.