Accurate PLL charge pump with matched up/down currents from Vds-compensated common-gate switches
US6124741A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 8, 1999 |
| Grant date | Sep 26, 2000 |
| Priority date | — |
| Expiry date | Mar 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/6872
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A more accurate charge pump reduces phase error in a PLL. An UP input pulse causes a p-channel drive transistor to charge a filter capacitor on the output, while a down DN input pulse causes an n-channel drive transistor to discharge the output. The drive transistors are connected to power or ground through a supply transistor. The supply transistor is biased on in the linear region and is not switched off. The sources of the drive transistors are always driven by the supply transistors, preventing phase error from floating sources. The drive transistors are common-gate switches with their gates biased by a compensating bias generator. The p-channel drive transistor current variations with Vds are compensated by providing a similar current variation to the n-channel drive transistor. Thus the bias is adjusted to compensate for drain-source voltage changes that can cause the up and down currents from the drive transistors to mismatch. The drive transistors are switched on and off by the up and down input pulses by current sources that steer additional current through the supply transistors. The additional current raises the n-channel drive transistor source to turn off the down curr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.