Wide bandwidth frequency multiplier
US6124742A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1998 |
| Grant date | Sep 26, 2000 |
| Priority date | — |
| Expiry date | Jan 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03B19/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A wide bandwidth frequency multiplier (48) multiplies a first frequency of an input signal (52) to generate an output signal (54) having a second frequency. The multiplier (48) includes first stage doubler (56). The doubler (56) includes a lumped element power splitter (62), a push-push amplifier (80), and a combining junction (96). The power splitter (62) splits the input signal (52) into first and second signals (70, 72) that are balanced in phase. A series resistive element (86) maintains amplitude balance between the first and second signals (70, 72). First and second feedback circuits (166, 184) are integrated with first and second transistors (164, 182) so that the push-push amplifier (80) operates over wide bandwidth. In addition, the multiplier (48) includes a second stage doubler (58) configured similar to the first stage doubler (56) for producing an output signal (54) that is quadruple the frequency of input signal (52). The first and second stage doublers (56, 58) are combined on a single integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.