Semiconductor structure for long-term learning
US6125053A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1998 |
| Grant date | Sep 26, 2000 |
| Priority date | — |
| Expiry date | Nov 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pMOS EEPROM cell includes a source, drain, channel, control gate and well contact. The device is a fully functional single element p-type floating gate MOSFET. A floating gate overlaps the well contact and completely surrounds the drain and source implants. The pMOS cell is written to by means of hot-electron injection, using an intrinsic feedback mechanism to write analog values. Hot electrons are generated in the channel by means of hole impact ionization at the transistor's drain. The pMOS cell is erased by Fowler-Nordheim tunneling. The tunneling voltage is applied only to the well to tunnel electrons from the floating gate. The well-source and well-drain junctions are protected from breakdown by means of guard rings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.