Apparatus and method for providing a quiet time before analog signal sampling in a mixed signal integrated circuit employing synchronous and asynchronous clocking
US6125077A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1999 |
| Grant date | Sep 26, 2000 |
| Priority date | — |
| Expiry date | Apr 20, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mixed signal integrated circuit is provided having analog and digital circuits coupled to receive respective analog and digital clocking signals. The analog circuit portion may involve switched capacitors which charge and discharge based on timing of the analog clocking signal. The critical sampling moments mandated by the analog clocking signal are purposefully delayed after a quiet time so that pre-existing, digitally induced noise does not impute error in the sampled or loaded voltages. A clocking generator is therefore presented which delays rising edges of the digital clocking signal from falling edges of the analog clocking signal. The amount of delay is chosen to ensure that asynchronously generated noise arising from the digital clocking signal does not substantially affect the critical sampled or loaded voltages. The digital circuit portion can therefore include a memory element having transitory bit lines and a sense amplifier coupled to receive voltages on those bit lines. The effect of noise introduced by the transitory bit lines and the operable sense amplifiers is minimized by designing the digital clocking signal leading edge to be delayed a fraction of 1/(2(N/M)) …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.