Non-buffered, non-blocking multistage ATM switch
US6125112A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 1998 |
| Grant date | Sep 26, 2000 |
| Priority date | — |
| Expiry date | Mar 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multistage ATM switch, method and system with switch elements with two input/outputs switchable to two other input/outputs. The switch elements are arranged connected to define a matrix with an input stage an output stage and at least one an intermediate stage. The multi stage switch inputs are presented with address information for data, the address information indicates requests for one of several outputs of said the multi stage switch. The requests are broadcast into the multi stage switch. At each stage the requests are remembered, merged and propagated to connected switching elements of a next stage. At each output of the multi stage switch grants a request if traffic can be accepted and propagates the requested grant to connected switching elements. At each switching element, upon receiving a request grant, the request grant is propagated to an input that requested the granted output port. If both inputs requested the granted port the switch element randomly chooses one of the two inputs and propagates the grant on the randomly chosen input. Upon receiving a request grant at an input of the multi stage switch, data is transmitted on a next time slot.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.