Method and device for communicating across a chip boundary including a serial-parallel data packet converter having flow control logic
US6125416A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 1997 |
| Grant date | Sep 26, 2000 |
| Priority date | — |
| Expiry date | Oct 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A single chip integrated circuit device includes a bus system for effecting communication of parallel data on chip, functional circuitry connected to the bus system for executing an operation in response to parallel data received from the bus system, an external port, and a serial to parallel data packet converter interconnecting the parallel bus system and the external port. The external port includes a serial data input connector and a serial data output connector for supplying serial data packets between an external device and the integrated circuit device. The serial data packets each include a packet identifier indicating the length of the data packet and information defining an operation to be executed by the functional circuitry. The serial to parallel data packet converter is operable to read the packet identifier to determine the length of serial packets which are input through the port and to convert them into parallel data for supply in a forward direction to the bus system, such that if the serial data packet has a length which exceeds the bus width, the serial data packet is converted into successive sets of parallel data and placed sequentially on the bus system. The …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.