DRAM parity protection scheme
US6125466A · kind A · utility
20Cited by
13References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 28, 1994 |
| Grant date | Sep 26, 2000 |
| Priority date | — |
| Expiry date | Nov 28, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A scheme for protecting memory stored in a DRAM using a combination of horizontal and vertical parity data to detect and correct errors in a protected space of memory in which code is stored. The DRAM memory of this scheme is architected with the code stored in horizontally contiguous bytes and the vertical parity, generated when the code is compiled, also stored in horizontally contiguous bytes, but in a row of DRAM memory separate from those in which the code is stored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.