Manufacturing method for a capacitor in an integrated storage circuit

US6127220A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Gerrit Lange · Denzlingen, DE
• Martin Franosch · Munich, DE
• Volker Lehmann · Hersbruck, DE
• Hans Reisinger · Grünwald, DE
• Herbert Schafer · Höhenkirchen-Siegertsbrunn, DE
• Reinhard Stengl · Stadtbergen, DE
• Hermann Wendt · Grasbrunn, DE

Key dates

• Filing date: May 14, 1999
• Grant date: Oct 3, 2000
• Expiry date: May 14, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/318

Abstract

On a carrier a layer sequence is applied which contains alternatingly layers made of a first conducting material and a second material in which both materials are different from a carrier material. An opening is made in the layer sequence, which is filled with a conducting material so that a central supporting structure is produced. Then the layer sequence is structured corresponding to the dimensions of a capacitor and the layers made of the second material are removed selectively, so that a first capacitor electrode is formed. The layer sequence may have especially p.sup.+ -/p.sup.- silicon layers or silicon/germanium layers. An etch-stop layer can also be incorporated as the lowest or second-lowest layer.