Memory cell having implanted region formed between select and sense transistors
US6127225A · kind A · utility
5Cited by
5References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1999 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Dec 10, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector provides electrons for substrate hot electron injection of electrons onto the floating gate for programming. The cell depletion/inversion region may be extended by forming a capacitor as an extension of the control gate over the substrate between the source and channel of said sense transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.