Process of forming an EEPROM device having a split gate

US6127229A · kind A · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Wen-Ting Chu
• Di-Son Kuo · Hsinchu, TW
• Hung-Cheng Sung
• Jack Y. Yeh · North Potomac, US
• Chia-Ta Hsieh · Tainan, TW
• Yai-Fen Lin · Taichung, TW

Key dates

• Filing date: Apr 29, 1999
• Grant date: Oct 3, 2000
• Expiry date: Apr 29, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/30

Abstract

There is presented an improved method of fabricating an EEPROM device with a split gate. In the method, a silicon substrate is provided having spaced and parallel recessed oxide regions that isolate component regions where the oxide regions project above the top surface of the substrate. A thin gate oxide is formed on the substrate, and a first conformal layer is deposited over the gate oxide and projecting oxide regions. The substrate is then chemical-mechanically polished to remove the projections of polysilicon over the oxide regions. A silicon nitride layer is deposited on the resultant planar surface of the polysilicon, and elongated openings formed that will define the position of the floating gates that are perpendicular to the oxide regions. The exposed polysilicon in the openings in the silicon nitride are oxidized down to at least the level of the underlying silicon oxide regions, and the silicon nitride layer removed. The polysilicon layer is then removed using the silicon oxide layer as an etch barrier, and the edge surfaces of the resulting polysilicon floating gates oxidized. A second polysilicon layer is deposited on the substrate and elongated word lines formed that…