Method of manufacturing semiconductor device
US6127244A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 23, 1998 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Dec 23, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a SOI wafer using an isolation film as a polishing stopper, comprising the steps of: preparing a first and a second silicon substrates; implanting impurities into selected active regions of the first silicon substrate to a desired depth; etching the portion of the silicon substrate between the active regions to forming trenches having a desired depth; forming a first insulating layer of an oxide film on the first silicon substrate to be filled in the trenches; etching-back the first insulating layer to form a trench type isolation film; forming a second insulating layer of an oxide film on the first silicon substrate including the isolation film; bonding the first and the second silicon substrates to contact the second insulating layer with the second silicon substrate; firstly polishing the first silicon substrate by the vicinity of the portion of the first silicon substrate where the impurities are implanted; etching the polished first silicon substrate by using an etchant until the portion of the first silicon substrate where the impurities are implanted is removed; and secondarily polishing the first silicon substrate using the isolation film as a polish…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.