Process for fabricating a semiconductor device with a patterned metal layer
US6127268A · kind A · utility
3Cited by
8References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 11, 1998 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Jun 11, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A process is disclosed for fabricating a semiconductor device with a patterned metal layer (9). A layer (7) of a material with poor adhesion capability to the metal is deposited on the surface of a semiconductor substrate. On the layer (7), pattern lines (8) separated by a distance a are formed of a material with good adhesion capability to the metal, and the metal layer (9) is deposited such that by suitable choice of the ratio of the distance a to its thickness d and of its material properties, the metal layer (9) is caused to adhere only to the pattern lines (8) and to the area of the layer (7) between the pattern lines (8).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.