Structure of SRAM cell and method for fabricating the same

US6127704A · kind A · utility

Inventor

• Dong Sun Kim · Seoul, KR

Key dates

• Filing date: Mar 17, 1998
• Grant date: Oct 3, 2000
• Expiry date: Mar 17, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/12

Abstract

A CMOS SRAM cell includes a substrate divided by a well trench into an n well region and a p well region, first and second active regions each having a V shape, formed symmetrical relative to each other, and having the well trench in between, third and fourth active regions formed symmetrically relative to each other and offset from the second active region, first and second gate lines each crossing the first active region, the well trench, and the second active region, and a third gate line crossing the third and fourth active regions.