Test carrier for attaching a semiconductor device
US6127833A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1999 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Jan 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73265
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for forming a semiconductor test carrier including an insulating substrate having a top surface, a bottom surface, periphery; with a rectangular cavity centrally located on the top surface and extending through to the bottom surface. A conductive ground trace formed on the top surface at the periphery of the cavity with conductive corner power traces formed adjacent each corner of the ground trace, with a ruled pattern of conductive wire bond pads encircling the corner power traces. Wire bond pads are formed in a linear array on each of the four sides encircling the power traces. A first interstitial ball pad array encircles the conductive wire bond pads and connects with the bottom surface by way of conductive vias communicating with a second interstitial ball pad array at the bottom surface. A glass plate is attached to the underside of the insulated substrate to form a bottom supporting surface in the rectangular cavity. A semiconductor device is placed in the cavity and its backside adhesively bonded to the glass plate. The appropriate input/output terminals of the device are connected to appropriate wire bond pads and traces on the top surface of the substrate with me…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.