Semiconductor memory device including a clocking circuit for controlling the read circuit operation
US6128248A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1999 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Jul 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is provided which includes a memory cell array, a read circuit which reads data from said memory cell array, and an external terminal which receives an external clock signal. A first input circuit receives the external clock signal and outputs a first internal clock signal delayed from the external clock signal. A second input circuit receives the first internal clock signal and outputs a second internal clock signal delayed from the first internal clock signal. The memory device also includes a circuit which counts a clock signal having a frequency higher than that of the external clock signal and a circuit which starts the counting in response to the second internal clock signal, reverses the direction of said counting in response to the first internal clock signal and detects when a count of said counting circuit again reaches the count at the start of said counting, thereby outputting a timing signal therefrom. A clock output circuit is provided which outputs a third internal clock signal for controlling the operation of said read circuit based on the timing signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.