Method and system for interfacing parallelly interfaced devices through a serial bus
US6128311A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1998 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Feb 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for interconnecting via a serial bus a master processor and a co-processor having directly interfaceable parallel interfaces thereby accommodating the remote location of the co-processor from the master processor. The master processor interfaces with a serial bus interface for converting the parallel interface of the master processor into a serial interface forming a serial bus including a serial data out signal, a serial data in signal, a serial clock signal and a frame sync signal. The serial bus interfaces with the remote module having the co-processor located therein. The serial bus interfaces directly with an interface controller for converting the serial information back to a parallel format compatable with the requirements of the co-processor's parallel interface. The interface controller is further capable of generating control signals such as resets and general purpose outputs when directed by the master processor and reading status of the co-processor when also directed by the master processor. Testing functionality is also included for specific incorporation of an ISDN-specific I/O interface device functioning as the co-processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.