Memory device having plurality of flash memories with a flash memory controlling circuit
US6128675A · kind A · utility
19Cited by
39References
52Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 10, 1998 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Apr 10, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device with a small computer system interface reads and writes mass data at high speed. The memory device includes a plurality of flash memories and a control circuit for allowing the flash memories to write and read data by page and to erase the data by block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.