Apparatus and method for a base address register on a computer peripheral device supporting configuration and testing of address space size
US6128718A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1997 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Aug 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/342
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for providing a base address register in a computer system that allows the length of the base address portion of an address to be changed and thereby allows various sizes of address spaces to be supported by the same base address register. The method employs steps that enable and disable bits of the base address register to properly support the desired address space size. Some embodiments of the method set disabled bits of the base address register to a known value. An apparatus that employs the method includes a second register connected to the base address register to supply signals that enable and disable bits of the base address register appropriately.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.