Fault-tolerant multiple processor system with signature voting
US6128755A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 1994 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Aug 25, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/83
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor computer system and associated method having processing error detection capability is disclosed for error-free processing of an instruction set. The instruction set is replicated and processed substantially in parallel through a plurality of processing nodes of the computer system. Each processing node collects a compressed hardware signature commensurate with and derived from the execution of the instruction set. Subsequent instruction set processing, the collected hardware signatures from each processing node are compared and the presence or absence of a processing error is determined with reference to a predetermined voting scheme. Processing of the instruction sets through the plurality of processing nodes is typically asynchronous with synchronization occurring subsequent each processor's execution of the instruction set, such that each processor can be driven by an independent clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.