Radiation hardened dielectric for EEPROM
US6130172A · kind A · utility
6Cited by
9References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 16, 1998 |
| Grant date | Oct 10, 2000 |
| Priority date | — |
| Expiry date | Apr 16, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/953
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A EEPROM 140 has a storage transistor 160 with a gate insulating layer 104 of BPSG and a polysilicon gate 112.2 of the same layer as the polysilicon gate 112.1 of the FET transistor 150. The BPSG layer 104 has POHC traps that capture holes injected into N well 103.2. A positive voltage applied to N well 103.2 programs the storage transistor 160 off. Applying a positive voltage to the gate 112.2 neutralizes the holes stored in layer 104 and erases the memory of transistor 160.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.