Signal converting receiver having constant hysteresis, and method therefor
US6130548A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 9, 1999 |
| Grant date | Oct 10, 2000 |
| Priority date | — |
| Expiry date | Jul 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0276
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A LVDS receiver (200) converts a differential input signal (15) at an input (201/202, e.g., voltage difference V.sub.1 -V.sub.2) to a single output signal (20) at an output (295). The receiver (200) has a signal distributor (205), first and second transistor pairs (220,210), a combiner (260), and an output trigger (250). The distributor (205) either forwards the differential input signal (15) to the first transistor pair (220) when the common mode portion of the input signal (15, e.g., V.sub.CM =(V.sub.1 +V.sub.2)/2) of the first and second input signal components is in a first magnitude range (e.g., V.sub.CM >V.sub.REF) or to the second transistor pair (210) when the common mode portion is in a second, different magnitude range (e.g., V.sub.CM <V.sub.REF). The transistors of both pairs (210 and 220) are of the same conductivity type. This approach provides substantially constant input transconductances (g.sub.m) over the whole common mode input signal range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.