Programmable function block
US6130553A · kind A · utility
Assignees
Inventor
Key dates
| Filing date | Oct 13, 1998 |
| Grant date | Oct 10, 2000 |
| Priority date | — |
| Expiry date | Oct 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable function block 20 comprises a logic block 21 including a full adder 31 and at least one preposition logic 32, and an input block 22 including programmable input switch units 40-1 through 40-9 for use in selectively switching a HIGH logic level signal, a LOW logic level signal, and a signal on interconnection lines 50. The preposition logic 32 comprises an exclusive OR circuit 32-1 and a multiplexer 32-2 and functions as various different logic circuits by means of setting some of the inputs thereof to a HIGH logic level or a LOW logic level. Thus, the logic block functions as various different logic circuits depending on the state of the inputs. In addition, the full adder provides fast arithmetic operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.