Patent · US Expired

Integrated circuit I/O buffer with 5V well and passive gate voltage

US6130556A · kind A · utility

48Cited by

15References

15Claims

0Family size

Assignee

LSI Logic Corporation · US

Inventors

Jonathan Schmitt · Eden Prairie, US
Gary Hom · Berkeley Heights, US
Luong Hung · Cupertino, US

Key dates

Filing date	Jun 16, 1998
Grant date	Oct 10, 2000
Priority date	—
Expiry date	Jun 16, 2018

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/00315
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An integrated circuit buffer includes a core output terminal, a pad terminal, a pad pull-down transistor, a pad pull-up transistor, a pull-down control circuit and a pull-up control circuit. The pad pull-down transistor and the pad pull-up transistor are coupled to the pad terminal and have pull-up and pull-down control terminals, respectively. The pull-down control circuit is coupled between the core output terminal and the pull-down control terminal. The pull-up control circuit is coupled between the core output terminal and the pull-up control terminal. A pull-up voltage protection transistor is coupled in series between the pad pull-up transistor and the pad terminal and has a control terminal which is coupled to the pad terminal through a voltage feedback circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.