Method and apparatus for multi-level demand caching of textures in a graphics display device

US6130680A · kind A · utility

Assignee

• Intel Corporation · US

Inventors

• Michael Brian Cox · Menlo Park, US
• Michael J. Shantz · Cupertino, US

Key dates

• Filing date: Dec 1, 1997
• Grant date: Oct 10, 2000
• Expiry date: Dec 1, 2017

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T1/60
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A computer graphics system for caching textures includes an L3 memory, an L2 cache, and an L1 cache for storing such textures and also includes a graphics accelerator (GA) for mapping these stored textures onto primitives for graphics display. The L3 memory, which has the largest capacity also has the slowest retrieval speed, while the L1 cache has the smallest capacity and the quickest retrieval speed. The textures are divided into a plurality of L2 texture blocks and each L2 texture block is subdivided into a plurality of L1 sub-blocks. During its rendering process, the GA searches the L1 cache for a particular L1 sub-block that is to be applied to a primitive. If such L1 sub-block is stored within the L1 cache, the GA will extract the desired texels (i.e., texture pixels) from the L1 sub-block and apply such texels to the primitive. If the L1 sub-block is not located in the L1 cache, the GA will search the L2 cache for the L1 sub-block. If it is found in the L2 cache, the GA will load the L1 sub-block to the L1 cache. However, if the L1 sub-block is not found within the L2 cache, the GA will load the L1 sub-block from the L3 memory to both the L1 and L2 caches. Advantageously, w…